Semiconductor Die and Method of Forming through Organic Vias having Varying Width in Peripheral Region of the Die

ABSTRACT

A plurality of semiconductor die is mounted to a carrier separated by a peripheral region. An insulating material is deposited in the peripheral region. A first opening is formed in the insulating material of the peripheral region to a first depth. A second opening is formed in the insulating material of the peripheral region centered over the first opening to a second depth less than the first depth. The first and second openings constitute a composite through organic via (TOV) having a first width in a vertical region of the first opening and a second width in a vertical region of the second opening. The second width is different than the first width. A conductive material is deposited in the composite TOV to form a conductive TOV. An organic solderability preservative (OSP) coating is formed over a contact surface of the conductive TOV.

CLAIM TO DOMESTIC PRIORITY

The present application is a continuation of U.S. patent applicationSer. No. 12/406,038, filed Mar. 17, 2009, which application isincorporated herein by reference.

FIELD OF THE INVENTION

The present invention relates in general to semiconductor devices and,more particularly, to a semiconductor die and method of forming throughorganic vias having varying width in a peripheral region of the die.

BACKGROUND OF THE INVENTION

Semiconductor devices are commonly found in modern electronic products.Semiconductor devices vary in the number and density of electricalcomponents. Discrete semiconductor devices generally contain one type ofelectrical component, e.g., light emitting diode (LED), transistor,resistor, capacitor, inductor, and power metal oxide semiconductor fieldeffect transistor (MOSFET). Integrated semiconductor devices typicallycontain hundreds to millions of electrical components. Examples ofintegrated semiconductor devices include microcontrollers,microprocessors, charged-coupled devices (CCDs), solar cells, anddigital micro-mirror devices (DMDs).

Semiconductor devices perform a wide range of functions such ashigh-speed calculations, transmitting and receiving electromagneticsignals, controlling electronic devices, transforming sunlight toelectricity, and creating visual projections for television displays.Semiconductor devices are found in the fields of entertainment,communications, power generation, networks, computers, and consumerproducts. Semiconductor devices are also found in electronic productsincluding military, aviation, automotive, industrial controllers, andoffice equipment.

Semiconductor devices exploit the electrical properties of semiconductormaterials. The atomic structure of semiconductor material allows itselectrical conductivity to be manipulated by the application of anelectric field or through the process of doping. Doping introducesimpurities into the semiconductor material to manipulate and control theconductivity of the semiconductor device.

A semiconductor device contains active and passive electricalstructures. Active structures, including transistors, control the flowof electrical current. By varying levels of doping and application of anelectric field, the transistor either promotes or restricts the flow ofelectrical current. Passive structures, including resistors, diodes, andinductors, create a relationship between voltage and current necessaryto perform a variety of electrical functions. The passive and activestructures are electrically connected to form circuits, which enable thesemiconductor device to perform high-speed calculations and other usefulfunctions.

Semiconductor devices are generally manufactured using two complexmanufacturing processes, i.e., front-end manufacturing, and back-endmanufacturing, each involving potentially hundreds of steps. Front-endmanufacturing involves the formation of a plurality of die on thesurface of a semiconductor wafer. Each die is typically identical andcontains circuits formed by electrically connecting active and passivecomponents. Back-end manufacturing involves singulating individual diefrom the finished wafer and packaging the die to provide structuralsupport and environmental isolation.

One goal of semiconductor manufacturing is to produce smallersemiconductor devices. Smaller devices typically consume less power,have higher performance, and can be produced more efficiently. Inaddition, smaller semiconductor devices have a smaller footprint, whichis desirable for smaller end products. A smaller die size may beachieved by improvements in the front-end process resulting in die withsmaller, higher density active and passive components. Back-endprocesses may result in semiconductor device packages with a smallerfootprint by improvements in electrical interconnection and packagingmaterials.

The vertical electrical interconnection between stacked semiconductorpackages can be accomplished with conductive through silicon vias (TSV)or through hole vias (THV). The THVs are typically made with copper andformed in organic materials in a peripheral region around the device.When interconnecting stacked semiconductor die, the small size of theTHV makes it difficult to properly align the THV with its matingsurface. Improper alignment can cause device defects. Manufacturersoften use high-precision bonding equipment to achieve adequate yield,but such equipment adds significant manufacturing cost to the product.In addition, the copper-filled THV can oxidize which reduces adhesionstrength and increases contact resistance between bonded vias,particularly in the presence of high temperature and high pressureduring die stacking.

SUMMARY OF THE INVENTION

A need exists to electrically interconnect semiconductor die in thevertical direction. Accordingly, in one embodiment, the presentinvention is a method of making a semiconductor device comprising thesteps of providing a semiconductor die, depositing an insulatingmaterial in a peripheral region around the semiconductor die, andforming a plurality of conductive vias partially through the insulatingmaterial. The conductive vias include a first width in a first verticalregion of the insulating material and a second width different from thefirst width in a second vertical region of the insulating material. Themethod further includes the step of forming a first conductive layerbetween a first one of the conductive vias and a contact pad of thesemiconductor die.

In another embodiment, the present invention is a method of making asemiconductor device comprising the steps of providing a semiconductordie, depositing a first insulating material in a peripheral regionaround the semiconductor die, and forming a first conductive via in thefirst insulating material. The first conductive via includes a firstwidth and a second width different from the first width within the firstinsulating material. The method further includes the step of forming aconductive layer over a surface of the semiconductor die andelectrically connected to the first conductive via.

In another embodiment, the present invention is a method of making asemiconductor device comprising the steps of providing a semiconductordie, depositing an insulating material in a peripheral region around thesemiconductor die, and forming a first conductive via partially throughthe insulating material. The first conductive via includes a first widthand a second width different from the first width within the firstinsulating material.

In another embodiment, the present invention is a semiconductor devicecomprising a semiconductor die and insulating material deposited in aperipheral region around the semiconductor die. A conductive via isformed partially through the insulating material. The conductive viaincludes different widths within the insulating material.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a printed circuit board (PCB) with different types ofpackages mounted to its surface;

FIGS. 2 a-2 c illustrate further detail of the representativesemiconductor packages mounted to the PCB;

FIGS. 3 a-3 f illustrate a process of forming through organic vias (TOV)having varying width in a peripheral region of a semiconductor die;

FIG. 4 illustrates the semiconductor die with TOVs having varying widthformed in the peripheral region of the die;

FIG. 5 illustrates two stacked semiconductor die with TOVs havingvarying width formed in the peripheral region of the die;

FIG. 6 illustrates another embodiment of the semiconductor die with TOVshaving varying width formed in the peripheral region of the die;

FIG. 7 illustrates two stacked semiconductor die with TOVs havingvarying width from FIG. 6;

FIG. 8 is a top view of the semiconductor die with TOVs having varyingwidth formed in the peripheral region of the die;

FIG. 9 illustrates two stackable semiconductor die with TOVs havingvarying width and an OSP coating;

FIG. 10 illustrates the semiconductor die with multiple rows of TOVshaving varying width formed in the peripheral region of the die;

FIG. 11 illustrates the semiconductor die with TOVs having varying widthextending above and below the organic material formed in the peripheralregion of the die;

FIG. 12 illustrates the semiconductor die with TOVs having varying widthrecessed in the organic material;

FIG. 13 illustrates the semiconductor die with TOVs having varying widthand through silicon vias;

FIG. 14 illustrates the semiconductor die with TOVs having varying widthand backside RDLs; and

FIG. 15 illustrates the semiconductor die with conformally applied TOVshaving varying width formed in the peripheral region of the die.

DETAILED DESCRIPTION OF THE DRAWINGS

The present invention is described in one or more embodiments in thefollowing description with reference to the Figures, in which likenumerals represent the same or similar elements. While the invention isdescribed in terms of the best mode for achieving the invention'sobjectives, it will be appreciated by those skilled in the art that itis intended to cover alternatives, modifications, and equivalents as maybe included within the spirit and scope of the invention as defined bythe appended claims and their equivalents as supported by the followingdisclosure and drawings.

Semiconductor devices are generally manufactured using two complexmanufacturing processes: front-end manufacturing and back-endmanufacturing. Front-end manufacturing involves the formation of aplurality of die on the surface of a semiconductor wafer. Each die onthe wafer contains active and passive electrical components, which areelectrically connected to form functional electrical circuits. Activeelectrical components, such as transistors, have the ability to controlthe flow of electrical current. Passive electrical components, such ascapacitors, inductors, resistors, and transformers, create arelationship between voltage and current necessary to perform electricalcircuit functions.

Passive and active components are formed over the surface of thesemiconductor wafer by a series of process steps including doping,deposition, photolithography, etching, and planarization. Dopingintroduces impurities into the semiconductor material by techniques suchas ion implantation or thermal diffusion. The doping process modifiesthe electrical conductivity of semiconductor material in active devices,transforming the semiconductor material into a permanent insulator,permanent conductor, or changing the semiconductor material conductivityin response to an electric field. Transistors contain regions of varyingtypes and degrees of doping arranged as necessary to enable thetransistor to promote or restrict the flow of electrical current uponthe application of an electric field.

Active and passive components are formed by layers of materials withdifferent electrical properties. The layers can be formed by a varietyof deposition techniques determined in part by the type of materialbeing deposited. For example, thin film deposition may involve chemicalvapor deposition (CVD), physical vapor deposition (PVD), electrolyticplating, and electroless plating processes. Each layer is generallypatterned to form portions of active components, passive components, orelectrical connections between components.

The layers can be patterned using photolithography, which involves thedeposition of light sensitive material, e.g., photoresist, over thelayer to be patterned. A pattern is transferred from a photomask to thephotoresist using light. The portion of the photoresist patternsubjected to light is removed using a solvent, exposing portions of theunderlying layer to be patterned. The remainder of the photoresist isremoved, leaving behind a patterned layer. Alternatively, some types ofmaterials are patterned by directly depositing the material into theareas or voids formed by a previous deposition/etch process usingtechniques such as electroless and electrolytic plating.

Depositing a thin film of material over an existing pattern canexaggerate the underlying pattern and create a non-uniformly flatsurface. A uniformly flat surface is required to produce smaller andmore densely packed active and passive components. Planarization can beused to remove material from the surface of the wafer and produce auniformly flat surface. Planarization involves polishing the surface ofthe wafer with a polishing pad. An abrasive material and corrosivechemical are added to the surface of the wafer during polishing. Thecombined mechanical action of the abrasive and corrosive action of thechemical removes any irregular topography, resulting in a uniformly flatsurface.

Back-end manufacturing refers to cutting or singulating the finishedwafer into the individual die and then packaging the die for structuralsupport and environmental isolation. To singulate the die, the wafer isscored and broken along non-functional regions of the wafer called sawstreets or scribes. The wafer is singulated using a laser cutting deviceor saw blade. After singulation, the individual die are mounted to apackage substrate that includes pins or contact pads for interconnectionwith other system components. Contact pads formed over the semiconductordie are then connected to contact pads within the package. Theelectrical connections can be made with solder bumps, stud bumps,conductive paste, or wirebonds. An encapsulant or other molding materialis deposited over the package to provide physical support and electricalisolation. The finished package is then inserted into an electricalsystem and the functionality of the semiconductor device is madeavailable to the other system components.

FIG. 1 illustrates electronic device 10 having a chip carrier substrateor printed circuit board (PCB) 12 with a plurality of semiconductorpackages mounted on its surface. Electronic device 10 may have one typeof semiconductor package, or multiple types of semiconductor packages,depending on the application. The different types of semiconductorpackages are shown in FIG. 1 for purposes of illustration.

Electronic device 10 may be a stand-alone system that uses thesemiconductor packages to perform an electrical function. Alternatively,electronic device 10 may be a subcomponent of a larger system. Forexample, electronic device 10 may be a graphics card, network interfacecard, or other signal processing card that can be inserted into acomputer. The semiconductor package can include microprocessors,memories, application specific integrated circuits (ASICs), logiccircuits, analog circuits, RF circuits, discrete devices, or othersemiconductor die or electrical components.

In FIG. 1, PCB 12 provides a general substrate for structural supportand electrical interconnect of the semiconductor packages mounted on thePCB. Conductive signal traces 14 are formed over a surface or withinlayers of PCB 12 using evaporation, electrolytic plating, electrolessplating, screen printing, PVD, or other suitable metal depositionprocess. Signal traces 14 provide for electrical communication betweeneach of the semiconductor packages, mounted components, and otherexternal system components. Traces 14 also provide power and groundconnections to each of the semiconductor packages.

In some embodiments, a semiconductor device has two packaging levels.First level packaging is a technique for mechanically and electricallyattaching the semiconductor die to a carrier. Second level packaginginvolves mechanically and electrically attaching the carrier to the PCB.In other embodiments, a semiconductor device may only have the firstlevel packaging where the die is mechanically and electrically mounteddirectly to the PCB.

For the purpose of illustration, several types of first level packaging,including wire bond package 16 and flip chip 18, are shown on PCB 12.Additionally, several types of second level packaging, including ballgrid array (BGA) 20, bump chip carrier (BCC) 22, dual in-line package(DIP) 24, land grid array (LGA) 26, multi-chip module (MCM) 28, quadflat non-leaded package (QFN) 30, and quad flat package 32, are shownmounted on PCB 12. Depending upon the system requirements, anycombination of semiconductor packages, configured with any combinationof first and second level packaging styles, as well as other electroniccomponents, can be connected to PCB 12. In some embodiments, electronicdevice 10 includes a single attached semiconductor package, while otherembodiments call for multiple interconnected packages. By combining oneor more semiconductor packages over a single substrate, manufacturerscan incorporate pre-made components into electronic devices and systems.Because the semiconductor packages include sophisticated functionality,electronic devices can be manufactured using cheaper components and astreamlined manufacturing process. The resulting devices are less likelyto fail and less expensive to manufacture resulting in lower costs forconsumers.

FIG. 2 a illustrates further detail of DIP 24 mounted on PCB 12. DIP 24includes semiconductor die 34 having contact pads 36. Semiconductor die34 includes an active region containing analog or digital circuitsimplemented as active devices, passive devices, conductive layers, anddielectric layers formed within semiconductor die 34 and areelectrically interconnected according to the electrical design of thedie. For example, the circuit may include one or more transistors,diodes, inductors, capacitors, resistors, and other circuit elementsformed within the active region of die 34. Contact pads 36 are made witha conductive material, such as aluminum (Al), copper (Cu), tin (Sn),nickel (Ni), gold (Au), or silver (Ag), and are electrically connectedto the circuit elements formed within die 34. Contact pads 36 are formedby PVD, CVD, electrolytic plating, or electroless plating process.During assembly of DIP 24, semiconductor die 34 is mounted to a carrier38 using a gold-silicon eutectic layer or adhesive material such asthermal epoxy. The package body includes an insulative packagingmaterial such as polymer or ceramic. Conductor leads 40 are connected tocarrier 38 and wire bonds 42 are formed between leads 40 and contactpads 36 of die 34 as a first level packaging. Encapsulant 44 isdeposited over the package for environmental protection by preventingmoisture and particles from entering the package and contaminating die34, contact pads 36, or wire bonds 42. DIP 24 is connected to PCB 12 byinserting leads 40 into holes formed through PCB 12. Solder material 46is flowed around leads 40 and into the holes to physically andelectrically connect DIP 24 to PCB 12. Solder material 46 can be anymetal or electrically conductive material, e.g., Sn, lead (Pb), Au, Ag,Cu, zinc (Zn), bismuthinite (Bi), and alloys thereof, with an optionalflux material. For example, the solder material can be eutectic Sn/Pb,high-lead, or lead-free.

FIG. 2 b illustrates further detail of BCC 22 mounted on PCB 12.Semiconductor die 47 is connected to a carrier by wire bond style firstlevel packaging. BCC 22 is mounted to PCB 12 with a BCC style secondlevel packaging. Semiconductor die 47 having contact pads 48 is mountedover a carrier using an underfill or epoxy-resin adhesive material 50.Semiconductor die 47 includes an active region containing analog ordigital circuits implemented as active devices, passive devices,conductive layers, and dielectric layers formed within semiconductor die47 and are electrically interconnected according to the electricaldesign of the die. For example, the circuit may include one or moretransistors, diodes, inductors, capacitors, resistors, and other circuitelements formed within the active region of die 47. Contact pads 48 aremade with a conductive material, such as Al, Cu, Sn, Ni, Au, or Ag, andare electrically connected to the circuit elements formed within die 47.Contact pads 48 are formed by PVD, CVD, electrolytic plating, orelectroless plating process. Wire bonds 54 and bond pads 56 and 58electrically connect contact pads 48 of semiconductor die 47 to contactpads 52 of BCC 22 forming the first level packaging. Molding compound orencapsulant 60 is deposited over semiconductor die 47, wire bonds 54,contact pads 48, and contact pads 52 to provide physical support andelectrical isolation for the device. Contact pads 64 are formed over asurface of PCB 12 using evaporation, electrolytic plating, electrolessplating, screen printing, PVD, or other suitable metal depositionprocess and are typically plated to prevent oxidation. Contact pads 64electrically connect to one or more conductive signal traces 14. Soldermaterial is deposited between contact pads 52 of BCC 22 and contact pads64 of PCB 12. The solder material is reflowed to form bumps 66 whichform a mechanical and electrical connection between BCC 22 and PCB 12.

In FIG. 2 c, semiconductor die 18 is mounted face down to carrier 76with a flip chip style first level packaging. BGA 20 is attached to PCB12 with a BGA style second level packaging. Active region 70 containinganalog or digital circuits implemented as active devices, passivedevices, conductive layers, and dielectric layers formed withinsemiconductor die 18 is electrically interconnected according to theelectrical design of the die. For example, the circuit may include oneor more transistors, diodes, inductors, capacitors, resistors, and othercircuit elements formed within active region 70 of semiconductor die 18.Semiconductor die 18 is electrically and mechanically attached tocarrier 76 through a large number of individual conductive solder bumpsor balls 78. Solder bumps 78 are formed over bump pads or interconnectsites 80, which are disposed on active region 70. Bump pads 80 are madewith a conductive material, such as Al, Cu, Sn, Ni, Au, or Ag, and areelectrically connected to the circuit elements formed in active region70. Bump pads 80 are formed by PVD, CVD, electrolytic plating, orelectroless plating process. Solder bumps 78 are electrically andmechanically connected to contact pads or interconnect sites 82 oncarrier 76 by a solder reflow process.

BGA 20 is electrically and mechanically attached to PCB 12 by a largenumber of individual conductive solder bumps or balls 86. The solderbumps are formed over bump pads or interconnect sites 84. The bump pads84 are electrically connected to interconnect sites 82 throughconductive lines 90 routed through carrier 76. Contact pads 88 areformed over a surface of PCB 12 using evaporation, electrolytic plating,electroless plating, screen printing, PVD, or other suitable metaldeposition process and are typically plated to prevent oxidation.Contact pads 88 electrically connect to one or more conductive signaltraces 14. The solder bumps 86 are electrically and mechanicallyconnected to contact pads or bonding pads 88 on PCB 12 by a solderreflow process. Molding compound or encapsulant 92 is deposited oversemiconductor die 18 and carrier 76 to provide physical support andelectrical isolation for the device. The flip chip semiconductor deviceprovides a short electrical conduction path from the active devices onsemiconductor die 18 to conduction tracks on PCB 12 in order to reducesignal propagation distance, lower capacitance, and improve overallcircuit performance. In another embodiment, the semiconductor die 18 canbe mechanically and electrically attached directly to PCB 12 using flipchip style first level packaging without carrier 76.

FIGS. 3 a-3 f illustrate a process of forming conductive vias in aperipheral region around a semiconductor die. To start the process, aplurality of semiconductor die 102 is formed on a semiconductor waferusing conventional integrated circuit processes, as described above.Each semiconductor die 102 includes analog or digital circuitsimplemented as active and passive devices, conductive layers, anddielectric layers formed on topside active surface 108 and electricallyinterconnected according to the electrical design of the die. Forexample, the circuit may include one or more transistors, diodes, andother circuit elements formed within active surface 108 to implementbaseband digital circuits, such as digital signal processor (DSP),memory, or other signal processing circuit. The semiconductor die 102may also contain integrated passive devices (IPD), such as inductors,capacitors, and resistor, for radio frequency (RF) signal processing.Contact pads 106 electrically connect to active and passive devices andsignal traces within active area 108 of semiconductor die 102.

Semiconductor die 102 are singulated from the wafer and transferred totemporary carrier 104 using a pick-and-place operation. Semiconductordie 102 are mounted over carrier 104 using ultraviolet (UV) tape with apredetermined separation or peripheral region to provide adequatespacing between the die to form through organic vias (TOV) or throughhole vias (THV), as described below. The front side of semiconductor die102 is affixed to carrier 104 with contact pads 106 and active surface108 oriented face down.

In an alternate embodiment, the semiconductor wafer, with semiconductordie 102 separated by a saw street, is mounted to an expansion table withUV tape. A saw blade or laser tool cuts through the saw street down tothe expansion table in a dicing operation. The expansion table moves intwo-dimension lateral directions to expand the width of the saw streetand form a peripheral region which creates a greater physical separationbetween the die. The expansion table moves substantially the samedistance in the x-axis and y-axis within the tolerance of the tablecontrol to provide separation around a periphery of each die.

An organic insulating material 110 is deposited in the peripheral regionbetween semiconductor die 102 using spin coating, needle dispensing, orother suitable application process. In one embodiment, organic material110 can be benzocyclobutene (BCB), polyimide (PI), or acrylic resin.Alternatively, other non-conductive materials such as a polymer moldingcompound, liquid epoxy molding, compression molding, soft laminatingfilm, or other material having dielectric or electrical insulatingproperties can be deposited in the peripheral region. The non-conductivematerials can also be deposited using a transfer molding or injectionmolding process.

In FIG. 3 b, the temporary carrier 104 is removed and the assembly isinverted so that contact pads 106 and active surface 108 face upward. Afirst portion of organic material 110 is removed by laser drilling ordeep reactive ion etching (DRIE) to a depth of 5-500 micrometers (μm) toform an opening or hole 112. In FIG. 3 c, a second portion of organicmaterial 110 is removed by laser drilling or DRIE to form an opening orhole 114 to a depth less than the depth of opening 112, e.g. less thanhalf the depth of opening 112. Alternatively, openings 112 and 114 areformed with wet or dry etching using different masks. Opening 114 iscentered over opening 112 but cut to a lesser depth. The combination ofopenings 112 and 114 form a composite T-shaped through organic viahaving varying widths as the width of opening 114 is greater than thewidth of opening 112. In one embodiment, the width of opening 112 is5-400 μm and the width of opening 114 is 2.5-200 μm. The sidewalls ofopening 112 and opening 114 can be vertical or tapered.

In FIG. 3 d, an electrically conductive material 116 is deposited intoopenings 112 and 114 to form conductive through organic vias (TOV) usingPVD, CVD, evaporation, electrolytic plating, electroless plating, screenprinting, or other suitable metal deposition process. TOVs 116 havevarying widths or diameters, i.e., the TOV has a first width in verticalregion 118 of organic material 110 and a second width in vertical region120 of organic material 110. The first width of TOV 116 in region 118 isgreater than the second width of the TOV in region 120. The larger widthof TOV 116 in region 118 provides greater alignment tolerance andsimplifies interconnection when stacking semiconductor die. The smallerwidth of TOV 116 in region 118 requires less conductive filling, whichdecreases manufacturing time. TOVs 116 can have tapered sidewalls whichalso simplifies the filling of the composite via with conductivematerial.

In FIG. 3 e, an electrically conductive layer 122 is patterned anddeposited over organic material 110 and active surface 108 ofsemiconductor die 102 using PVD, CVD, evaporation, electrolytic plating,electroless plating, screen printing, or other suitable metal depositionprocess. An optional passivation layer can be deposited oversemiconductor die 102 to isolate conductive layer 122 from activesurface 108. The passivation layer can be one or more layers of silicondioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON),tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), or other materialhaving similar insulating and structural properties. A portion of thepassivation layer is removed by an etching process to expose contactpads 106. The conductive layer 122 forms signal traces or redistributionlayers (RDL) to electrically connect contact pads 106 to TOVs 116. Theconductive material 116 and conductive layer 122 can be one or morelayers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electricallyconductive material.

In FIG. 3 f, the backside of semiconductor die 102 undergoes abackgrinding process to expose TOV 116. The backgrinding may involvemechanical grinding, CMP, wet etching, dry etching, plasma etching, oranother thinning process. Semiconductor die 102 are singulated through acenter portion of organic material 110 between TOVs 116. The organicmaterial 110 is cut by a cutting tool 126 such as a saw blade or laser.The cutting tool completely severs the peripheral region to separate thedie.

FIG. 4 shows a final configuration for semiconductor die 102 with TOVs116 having varying width, i.e., the topside of TOV 116 larger than thebottom-side of the TOV. Conductive TOVs 116 electrically connect throughRDLs 122 to contact pads 106 and electrical components within activesurface 108. Conductive TOVs 116 extend from one side of the peripheralregion of semiconductor die 102 to the opposite side of the device.Conductive TOVs 116 provide electrically interconnection in the vertical(z) direction when stacking semiconductor die.

FIG. 5 shows two stacked semiconductor die 102. Conductive TOVs 116 aremounted with electrically conductive bonding agent 128. The largerportion of TOV 116 in vertical region 118 increases alignment tolerancewith the smaller portion of TOV 116 in vertical region 120. The activesurfaces 108 of semiconductor die 102 electrically connect throughcontact pads 106, RDLs 122, and conductive TOVs 116.

An alternate embodiment of a semiconductor die with TOVs having varyingwidth is shown in FIG. 6. In this case, the bottom-side of the TOV islarger than the topside of the TOV. After the temporary carrier isremoved, as shown in FIG. 3 b, semiconductor die 130 remains orientedwith contact pads 132 and active surface 134 face down. A first openingor hole is formed in organic material 136 by laser drilling or DRIE to adepth of 5-500 μm. A second opening or hole is formed in organicmaterial 136 by laser drilling or DRIE to a depth less than the depth ofthe first opening, e.g. less than half the depth of the first opening.The second opening is centered over the first opening to form acomposite inverted T-shaped TOV. The openings can be formed with wet ordry etching using different masks. The width of the opening in verticalregion 140 is greater than the width of the opening in vertical region138. In one embodiment, the width of the opening in vertical region 140is 5-400 μm and the width of the opening in vertical region 138 is2.5-200 μm. The sidewalls of opening 112 and opening 114 can be verticalor tapered.

An electrically conductive material 142 is deposited into the openingsto form conductive TOV using PVD, CVD, evaporation, electrolyticplating, electroless plating, screen printing, or other suitable metaldeposition process. TOVs 142 have varying widths or diameters. In thiscase, TOV 142 has a first width in vertical region 140 of organicmaterial 136 and a second width in vertical region 138 of organicmaterial 136. The first width of TOV 142 in vertical region 140 isgreater than the second width of the TOV in vertical region 138. Thelarger width of TOV 142 in region 140 provides greater alignmenttolerance and simplifies interconnection when stacking semiconductordie. The smaller width of TOV 142 in region 138 requires less conductivefilling, which decreases manufacturing time. TOVs 142 can have taperedsidewalls which also simplifies conductive filling.

An electrically conductive layer 144 is patterned and deposited overorganic material 136 and active surface 134 of semiconductor die 130using PVD, CVD, evaporation, electrolytic plating, electroless plating,screen printing, or other suitable metal deposition process. An optionalpassivation layer can be deposited over semiconductor die 130 to isolateconductive layer 144 from active surface 134. The passivation layer canbe one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, or othermaterial having similar insulating and structural properties. A portionof the passivation layer is removed by an etching process to exposecontact pads 132. The conductive layer 144 forms signal traces or RDL toelectrically connect contact pads 132 to TOVs 142. The conductivematerial 142 and conductive layer 144 can be one or more layers of Al,Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material.

Semiconductor die 130 are singulated through a center portion of organicmaterial 136 between TOVs 142. The organic material 136 is cut by acutting tool such as a saw blade or laser. The cutting tool completelysevers the peripheral region to separate the die.

Conductive TOVs 142 electrically connect through RDLs 144 to contactpads 132. Conductive TOVs 142 extend from one side of the peripheralregion of semiconductor die 130 to the opposite side of the device.Conductive TOVs 142 provide electrically interconnection in thez-direction when stacking semiconductor die.

FIG. 7 shows two stacked semiconductor die 130. Conductive TOVs 142 aremounted with electrically conductive bonding agent 146. The largerportion of TOV 142 in vertical region 140 increases alignment tolerancewith the smaller portion of TOV 142 in vertical region 138. Theelectrical components within active surfaces 134 of semiconductor die130 electrically connect through contact pads 132, RDLs 144, andconductive TOVs 142.

FIG. 8 is a top view of semiconductor die 102 with TOVs 116. ConductiveTOVs 116 electrically connect through RDLs 122 to contact pads 106 andelectrical components within active surface 108. Conductive TOVs 116extend from one side of the peripheral region of semiconductor die 102to the opposite side of the device. Conductive TOVs 116 provideelectrically interconnection in the z-direction when stackingsemiconductor die.

In FIG. 9, two stackable semiconductor die 102 with conductive TOVs 116are shown prior to mounting. Many metals used in conductive TOVs, suchas Cu, readily oxidize. The Cu-oxide reduces adhesion strength andincreases contact resistance between bonded TOVs, particularly in thepresence of high temperature and high pressure during die stacking. Toreduce oxidation, an organic solderability preservative (OSP) coating148 is applied on upper and lower contact surfaces of TOVs 116. The OSPcoating 148 also improves adhesion and reduces contact resistancebetween bonded TOVs 116.

In one embodiment, the OSP coating 148 is formed by a series ofprocessing steps including acidic cleaning of the underlying Cu layer,water rinse, micro-etch, water rinse, acid clean, water rinse, airknife, apply OSP, air knife, low pressure water rinse, and drying toexpel moisture from the OSP coating and stabilize the materials. Themicro-etch can use a hydrogen-peroxide sulfuric acid. The Cu metal layermaintains a uniform and continuous OSP coating which completely fillsthe underlying surface. The immersion time is typically less than oneminute at a temperature range of 40-45° C. The pH of the operating OSPsolution should be maintained between 4.3 and 4.5.

The OSP solution may contain alkylimidazole, benzotriazole, rosin, rosinesters, or benzimidazole compounds, as described in U.S. Pat. No.5,173,130 and incorporated herein by reference. A typical benzimidazolecompound may have an alkyl group of at least three carbon atoms at the2-position dissolved in an organic acid. When the bare copper surface isimmersed in OSP solution, the benzimidazole compound in an organic acidis converted to a copper complex. The copper complex reacts with thebare copper surface and forms a layer of benzimidazole and coppercomplex. By incorporating copper ions in the aqueous solution of thebenzimidazole and acid, the reaction rate is enhanced.

Alternatively, the OSP coating can also be made with phenylimidazole orother imidazole compounds including 2-arylimidazole as the activeingredient, as described in U.S. Pat. No. 5,560,785 and incorporatedherein by reference. In any case, the OSP coating 148 is made about 0.35μm in thickness. The OSP coating 148 selectively protects the barecopper from oxidation, which if allowed to form could interfere with thesolderability of the core surfaces.

The OSP coated conductive TOVs 116 are bonded together with flux 150 toactivate OSP coating 148, as shown by arrows 152, under temperature(400° C.) and pressure (4000 mbar). The electrical components withinactive surfaces 108 of semiconductor die 102 electrically connectthrough contact pads 106, RDLs 122, and conductive TOVs 116.

FIG. 10 shows another embodiment of semiconductor die 102 with multiplerows of TOVs 116 having varying width, i.e., each with the topside ofthe TOV larger than the bottom-side of the TOV. The peripheral region ismade sufficiently wide to accommodate the multiple rows of TOVs 116having varying width. OSP coating 148 is applied to the upper and lowercontact surfaces of conductive TOVs 116 to reduce oxidation, improveadhesion, and lower contact resistance. Conductive TOVs 116 electricallyconnect through RDLs 122 to contact pads 106 and electrical componentswithin active surface 108. Conductive TOVs 116 extend from one side ofthe peripheral region of semiconductor die 102 to the opposite side ofthe device. Conductive TOVs 116 provide electrically interconnection inthe z-direction when stacking semiconductor die.

FIG. 11 shows another embodiment of semiconductor die 102 with TOVs 116having varying width, i.e., each with the topside of the TOV larger thanthe bottom-side of the TOV. OSP coating 148 is applied to the upper andlower contact surfaces of conductive TOVs 116 to reduce oxidation,improve adhesion, and lower contact resistance. Conductive TOVs 116electrically connect through RDLs 122 to contact pads 106 and electricalcomponents within active surface 108. Conductive TOVs 116 extend aboveone surface of organic material 110 in the peripheral region ofsemiconductor die 102 and further extend below the opposite surface oforganic material 110 in the peripheral region. The extensions ofconductive TOVs 116 above and below organic material 110 provideadditional vertical spacing between stacked semiconductor die.Conductive TOVs 116 provide electrically interconnection in thez-direction when stacking semiconductor die.

FIG. 12 shows another embodiment of semiconductor die 102 with TOVs 116having varying width, i.e., each with the topside of the TOV larger thanthe bottom-side of the TOV. OSP coating 148 is applied to the upper andlower contact surfaces of conductive TOVs 116 to reduce oxidation,improve adhesion, and lower contact resistance. Conductive TOVs 116electrically connect through RDLs 122 to contact pads 106 and electricalcomponents within active surface 108. The bottom-side of conductive TOVs116 is recessed in organic material 110 with respect to a back surfaceof semiconductor die 102. Conductive TOVs 116 provide electricallyinterconnection in the z-direction when stacking semiconductor die.

In FIG. 13, semiconductor die 102 is shown with TOVs 116 having varyingwidth, i.e., each with the topside of the TOV larger than thebottom-side of the TOV. OSP coating 148 is applied to the upper andlower contact surfaces of conductive TOVs 116 to reduce oxidation,improve adhesion, and lower contact resistance. Conductive TOVs 116electrically connect through RDLs 122 to contact pads 106 and electricalcomponents within active surface 108. Conductive TOVs 116 extend fromone side of the peripheral region of semiconductor die 102 to theopposite side of the device.

Semiconductor die 102 further includes through silicon vias (TSV) 154which electrically connect to contact pads 106 and electrical componentswithin active surface 108. TSVs 154 can be formed by etching or laserdrilling vias through the silicon area of semiconductor die 102. Thevias are filled with Al, Cu, Sn, Ni, Au, Ag, or other suitableelectrically conductive material using evaporation, electrolyticplating, electroless plating, screen printing, PVD, or other suitablemetal deposition process. Conductive TSVs 154 extend from one side ofsemiconductor die 102 to the opposite side of the device. ConductiveTOVs 116 and TSVs 154 provide electrically interconnection in thez-direction when stacking semiconductor die.

In FIG. 14, semiconductor die 102 is shown with TOVs 116 having varyingwidth, i.e., each with the topside of the TOV larger than thebottom-side of the TOV. OSP coating 148 is applied to the upper andlower contact surfaces of conductive TOVs 116 to reduce oxidation,improve adhesion, and lower contact resistance. Semiconductor die 102further includes backside RDL 158. RDL 158 can Al, Cu, Sn, Ni, Au, Ag,or other suitable electrically conductive material formed byevaporation, electrolytic plating, electroless plating, screen printing,PVD, or other suitable metal deposition process. Conductive TOVs 116electrically connect through RDLs 122 and 158 to contact pads 106 andelectrical components within active surface 108. Conductive TOVs 116extend from one side of the peripheral region of semiconductor die 102to the opposite side of the device. Conductive TOVs 116 provideelectrically interconnection in the z-direction when stackingsemiconductor die.

In FIG. 15, semiconductor die 102 is shown with TOVs having varyingwidth, i.e., each with the topside of the TOV larger than thebottom-side of the TOV. In this case, conductive layer 160 isconformally applied to openings 112 and 114, see FIG. 3 c. The remainingarea of openings 112 and 114 is filled with organic material 110. OSPcoating 148 is applied to the upper and lower contact surfaces ofconductive TOVs 160 to reduce oxidation, improve adhesion, and lowercontact resistance. Conductive TOVs 160 electrically connect throughRDLs 122 to contact pads 106 and electrical components within activesurface 108. Conductive TOVs 160 extend from one side of the peripheralregion of semiconductor die 102 to the opposite side of the device.Conductive TOVs 160 provide electrical interconnection in thez-direction when stacking semiconductor die.

While one or more embodiments of the present invention have beenillustrated in detail, the skilled artisan will appreciate thatmodifications and adaptations to those embodiments may be made withoutdeparting from the scope of the present invention as set forth in thefollowing claims.

1. A method of making a semiconductor device, comprising: providing asemiconductor die; depositing an insulating material in a peripheralregion around the semiconductor die; forming a plurality of conductivevias partially through the insulating material, the conductive viasincluding a first width in a first vertical region of the insulatingmaterial and a second width different from the first width in a secondvertical region of the insulating material; and forming a firstconductive layer between a first one of the conductive vias and acontact pad of the semiconductor die.
 2. The method of claim 1, whereinthe conductive vias extend from the insulating material.
 3. The methodof claim 1, wherein the conductive vias are recessed in the peripheralregion.
 4. The method of claim 1, further including forming an organicsolderability preservative (OSP) coating over a surface of theconductive vias.
 5. The method of claim 1, further including forming aplurality of rows of the conductive vias in the insulating material. 6.The method of claim 1, further including: stacking a plurality ofsemiconductor die; and electrically connecting the stacked semiconductordie through the conductive vias.
 7. A method of making a semiconductordevice, comprising: providing a semiconductor die; depositing a firstinsulating material in a peripheral region around the semiconductor die;forming a first conductive via in the first insulating material, thefirst conductive via including a first width and a second widthdifferent from the first width within the first insulating material; andforming a conductive layer over a surface of the semiconductor die andelectrically connected to the first conductive via.
 8. The method ofclaim 7, wherein the first width is less than half the second width. 9.The method of claim 7, wherein the first conductive via extends from thefirst insulating material.
 10. The method of claim 7, wherein the firstconductive via is recessed in the peripheral region.
 11. The method ofclaim 7, further including forming a second conductive via in an activearea of the semiconductor die, the second conductive via beingelectrically connected to the first conductive via.
 12. The method ofclaim 7, further including disposing a second insulating material withinthe first conductive via.
 13. The method of claim 7, further including:stacking a plurality of semiconductor die; and electrically connectingthe stacked semiconductor die through the first conductive via.
 14. Amethod of making a semiconductor device, comprising: providing asemiconductor die; depositing an insulating material in a peripheralregion around the semiconductor die; and forming a first conductive viapartially through the insulating material, the first conductive viaincluding different widths within the insulating material.
 15. Themethod of claim 14, further including forming a conductive layer over asurface of the semiconductor die and electrically connected to the firstconductive via.
 16. The method of claim 14, wherein the different widthsof the first conductive via include a first width less than half asecond width.
 17. The method of claim 14, wherein the first conductivevia extends from the insulating material.
 18. The method of claim 14,wherein the first conductive via is recessed in the peripheral region.19. The method of claim 14, further including forming a secondconductive via in an active area of the semiconductor die, the secondconductive via being electrically connected to one of the firstconductive via.
 20. The method of claim 14, further including: stackinga plurality of semiconductor die; and electrically connecting thestacked semiconductor die through the first conductive vias.
 21. Asemiconductor device, comprising: a semiconductor die; an insulatingmaterial deposited in a peripheral region around the semiconductor die;and a conductive via formed partially through the insulating material,the first conductive via including a first width and a second widthdifferent from the first width within the first insulating material. 22.The semiconductor device of claim 21, further including a conductivelayer formed over a surface of the semiconductor die and electricallyconnected to the conductive via.
 23. The semiconductor device of claim21, wherein the different widths of the conductive via include a firstwidth less than half a second width.
 24. The semiconductor device ofclaim 21, wherein the conductive via extends from the insulatingmaterial.
 25. The semiconductor device of claim 21, wherein theconductive via is recessed in the peripheral region.